C282 Systick

C282A1 Systick Sync: SoC frequency synchronization started

C282A2 Systick Sync: SoC frequency synchronization in progress, sample number: {unsigned} of 16

C282A3 Systick Sync: SoC frequency synchronization in progress, received 'SoC period' sample of: {float_4_4} [us]

C282A4 Systick Sync: SoC frequency synchronization in progress, received 'SoC ISR Latency' sample of: {float_3_5} [us]

C282A5 Systick Sync: SoC period determined to be: {float} [us]

C282A6 Systick Sync: SysTick timer LOAD value set to: {unsigned} [cpu-clock-cycles]

C282A7 Systick Sync: SoC frequency synchronization finished

C282A8 Systick Sync: SoC Phase synchronization started

C282A9 Systick Sync: SysTick<>SoC Phase error: {signed}

Negative number means the Systick counter was behind (too late), positive number means the Systick counter was ahead (too early)

C282A10 Systick Sync: Estimated Systick counter value at SoC: {unsigned}

C282A11 Systick Sync: Estimated Systick counter ticks to next SoC: {unsigned}

C282A12 Systick Sync: SoC Phase synchronization finished

C282A13 The internal SoC count value has been resynchronized with the FPGA SoC count. Data: {hex}

Data: [Number of resyncs, 16 bits][FPGA SoC count (new), 8 bit][Device SoC count (old), 8 bit]

C282A14 SOC status data failed to update in a timely manner